1. Technical Field
This invention relates in general to electronic circuits and, more particularly, to an electronic circuit with a configurable scan path.
2. Description of the Related Art
As circuit designs become denser and more complicated, the need for testing increases. Scan path testing, where test data is input to various circuit modules and the resultant output is compared to expected results, is one of the most powerful testing schemes. Unfortunately, scan path testing is one of the larger costs involved in manufacturing an electronic device.
To reduce scan path testing costs, low cost testers have been developed to reduce tester costs. Typically, however, the low cost testers are limited in function vis-à-vis more expensive testers, particularly in the number of scan chains that can be simultaneously tested at the most efficient mode of test operation for the tester.
Accordingly, the circuit designer must make a decision regarding whether to design a circuit with fewer, long scan chains for optimization of testing on a low cost tester, or a circuit with more, shorter scan chains for optimization of testing on a higher cost tester. This scenario places the designer in a difficult position, since it is most efficient to test many circuit designs on the low cost tester during the beginning stages (on die) and on the more expensive tester at later stages (packaged chip).
Therefore, a need has arisen for a circuit design that can be optimized for multiple testers.